AI Agent Workflow Collection

Author, compile, and validate analog behavioral models — Verilog-A, Verilog-AMS, VHDL-AMS, and SystemVerilog real-number models — plus the connect modules that bridge analog and digital domains. This is the analog-HDL core of the marketplace. Use when building a fast, accurate model of an analog block for AMS verification or system simulation.

Floorplan, generate matched devices, and place/route analog blocks with symmetry, shielding, and matching constraints to a clean, DRC-ready layout. Use when turning a sign-off-ready schematic into a GDS layout, or servicing a fixrequest that repairs the layout after a DRC/LVS or parasitic-degradation failure.

Solve the electromagnetics of an on-chip passive or antenna (inductor, transformer, transmission line, balun, antenna), extract a converged passive S-parameter model, and fit a lumped equivalent for circuit-level RF simulation. Use when building the passive model rf-design consumes, or to service an rf-design fixrequest (routeto: em-modeling) by re-solving the passive. Loop-backs are stage-local (passivity/fit → meshing/geometrydefinition); passivity is a hard gate; a fundamental geometry/stackup gap escalates.

Design and verify an RF/mmWave block (LNA, mixer, VCO, PLL, PA): topology selection and matching, S-parameter, harmonic-balance, Pnoise/PAC, IP3, and load-pull analyses, signed off against the RF spec table across corners. Use when designing or re-running an RF block. Loop-backs are stage-local first (spec/stability → topologymatching, convergence → harmonicbalance); when a cap is exhausted RF opens a cross-domain fixrequest (circuit-design for device rework, em-modeling for a passive shortfall) and reads the EM-modeling passive model as a data dependency.