About this skill
Build, explore, and verify Verilog/SystemVerilog RTL. Use when the user wants to write an RTL module, understand or review existing Verilog, or verify a design against a Python golden model with cocotb. Also extracts and diagrams control FSMs from the AST (deterministic, no hallucinated states) when a state diagram is explicitly wanted — but default to writing or reading Verilog, not diagramming.
Quick start
- Copy the install prompt. Use the green button above this README.
- Send it to your agent. Paste it into your coding agent’s chat and send.
- Review the setup. Your agent checks the skill’s instructions, requirements, and installation scope.
Review, license & listing details
This is an imported listing. We haven’t certified its safety, license, or compatibility. Skills may include executable scripts.
Only SKILL.md was scanned. Supporting files and scripts were not checked. No safety grade has been assigned.
0 potential findings · Scanned 11/4/2026 · Scanner 0.2.1
Content SHA-256: 4e9e227f62d57a17a84f78a3caa8db2c84a7d3b36836c2acb94d5d9d27f45c1c
About this listing
- Category
- Engineering
- Reported license
- MIT
- Listing language (estimated)
- English
- Review status
- Not individually reviewed
- Agent compatibility
- Atlas installation supports Claude Code, Codex, and Cursor. Skill-specific dependencies and features are checked during setup.