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Rtl Design

Agent skill
1 skill

SystemVerilog RTL design — module planning, coding standards enforcement, lint checking, CDC/RDC analysis, and synthesis readiness verification. Use when writing, reviewing, or debugging RTL for ASIC or FPGA targets, or when checking an existing RTL package for synthesis readiness.

Install with
Claude CodeCodexCursorGitHub CopilotGemini CLI

Supported by the Atlas install prompt. Skill-specific requirements vary.

Skill stats

Skills1CategoryEngineeringStars0

About this skill

SystemVerilog RTL design — module planning, coding standards enforcement, lint checking, CDC/RDC analysis, and synthesis readiness verification. Use when writing, reviewing, or debugging RTL for ASIC or FPGA targets, or when checking an existing RTL package for synthesis readiness.

Quick start

  1. Copy the install prompt. Use the green button above this README.
  2. Send it to your agent. Paste it into your coding agent’s chat and send.
  3. Review the setup. Your agent checks the skill’s instructions, requirements, and installation scope.
Review, license & listing details
Review the source before using this skill

This is an imported listing. We haven’t certified its safety, license, or compatibility. Skills may include executable scripts.

Automated security scan: Partial

Only SKILL.md was scanned. Supporting files and scripts were not checked. No safety grade has been assigned.

0 potential findings · Scanned 11/4/2026 · Scanner 0.2.1

Content SHA-256: 885956c0ca4a1e7dab4c3390b8ac77d75d2ead03c45a3e80334370737861e783

About scan coverage and limitations

About this listing

Category
Engineering
Reported license
MIT
Listing language (estimated)
English
Review status
Not individually reviewed
Agent compatibility
Atlas installation supports Claude Code, Codex, and Cursor. Skill-specific dependencies and features are checked during setup.
Rtl Design | Agent Skills Atlas