About this skill
Synthesize SystemVerilog/Verilog with Yosys. Reports area, timing, and resource utilization. Warns about unsupported SV constructs. Example: "synthesize my design for iCE40"
Quick start
- Copy the install prompt. Use the green button above this README.
- Send it to your agent. Paste it into your coding agent’s chat and send.
- Review the setup. Your agent checks the skill’s instructions, requirements, and installation scope.
Review, license & listing details
This is an imported listing. We haven’t certified its safety, license, or compatibility. Skills may include executable scripts.
Only SKILL.md was scanned. Supporting files and scripts were not checked. No safety grade has been assigned.
0 potential findings · Scanned 11/4/2026 · Scanner 0.2.1
Content SHA-256: 40ea9307430a3a63f603549e28b76f9a926d8707af0f98521e111c625449f4d8
About this listing
- Category
- General
- Reported license
- Not specified
- Listing language (estimated)
- English
- Review status
- Not individually reviewed
- Agent compatibility
- Atlas installation supports Claude Code, Codex, and Cursor. Skill-specific dependencies and features are checked during setup.