Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project.
EnglishParallel build orchestrator for SystemVerilog creation tasks. Decomposes designs into independent modules, builds in parallel phases, runs verification on each component, then integrates.
EnglishPython-based testbench generation using Cocotb. Alternative to SystemVerilog testbenches for Python-native hardware engineers.
EnglishError translation layer for hardware tool outputs. Converts cryptic Verilator, Yosys, GHDL, and simulation errors into 3-layer explanations. Used internally by gf orchestrator — not user-invocable directly.
EnglishExpand mode - asks clarifying questions, presents options with trade-offs, then hands off to appropriate skill/agent with enriched context.
EnglishFuseSoC build system integration for GateFlow. Generates .core files and drives synthesis/simulation through Edalize backends (Vivado, Quartus, open-source tools). Use when the user needs to create a FuseSoC core file, build with Edalize, or integrate RTL into a FuseSoC project.
EnglishIP block library manager. Install, list, and query verified drop-in hardware components. Each block includes RTL, testbench, formal properties, and documentation.
EnglishKiCad schematic and PCB generation from natural language. AI-verified drafts with DRC/ERC/AI review loop.
EnglishHardware design planner - Creates comprehensive RTL implementation plans. This skill should be used when the user wants to plan a new design, architect a complex feature, or understand how to implement hardware before coding.
EnglishPlace and route with nextpnr for open-source FPGA targets. Supports iCE40, ECP5, and Gowin devices.
EnglishManages .gateflow/project.yaml for project-specific configuration. Auto-detects project settings or prompts user for board, HDL, and target. Used internally by other skills — not typically invoked directly.
EnglishGateFlow release readiness workflow. Validates plugin manifests, marketplace metadata, docs index coverage, root mirrors, release notes, and component counts before a version tag is created. Use when preparing, checking, or cutting a GateFlow plugin release.
EnglishFigures out what kind of digital hardware design task the user wants to do, then hands off to the right specialist. Use when the request is unclear, multi-step, or needs help deciding whether to simulate, synthesize, lint, or implement.
EnglishSystemVerilog simulator with structured output for orchestration. Auto-detects DUT vs testbench, compiles with Verilator, runs simulation, and returns a parseable result block for /gf orchestration.
EnglishSummarize Verilator, lint, or simulation output into a readable, actionable format. Use when the user wants to understand build output, lint errors, or simulation results from a Verilator or EDA tool run.
EnglishSynthesize SystemVerilog/Verilog with Yosys. Reports area, timing, and resource utilization. Warns about unsupported SV constructs.
EnglishGateFlow terminal console inspired by OpenClaw local TUI workflows. Shows workspace status, component inventory, tool health, map readiness, release readiness, and command shortcuts from one terminal surface.
EnglishTerminal visualization for GateFlow codebase maps. Renders module hierarchies, FSM state diagrams, and module detail cards as interactive ASCII/Unicode art.
English
AGENT SKILLS ATLASIncludes Gf Architect, Gf Fusesoc, Gf Project, and other workflows.
Claude Code
Codex
Cursor
GitHub Copilot
Gemini CLISupported by the Atlas install prompt. Skill-specific requirements vary.
Pack stats
What’s included
Gf Architect
Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Example requests: "map this codebase", "document the architecture", "show module hierarchy"
Gf Build
Parallel build orchestrator for SystemVerilog creation tasks. Decomposes designs into independent modules, builds in parallel phases, runs verification on each component, then integrates. Example: "/gf-build RISC-V CPU with ALU, regfile, decoder, control FSM"
Gf Cocotb
Python-based testbench generation using Cocotb. Alternative to SystemVerilog testbenches for Python-native hardware engineers. Example: "create a cocotb test for the FIFO", "write Python testbench"
Gf Errors
Error translation layer for hardware tool outputs. Converts cryptic Verilator, Yosys, GHDL, and simulation errors into 3-layer explanations. Used internally by gf orchestrator — not user-invocable directly.
Gf Expand
Expand mode - asks clarifying questions, presents options with trade-offs, then hands off to appropriate skill/agent with enriched context.
Gf Fusesoc
FuseSoC build system integration for GateFlow. Generates .core files and drives synthesis/simulation through Edalize backends (Vivado, Quartus, open-source tools). Use when the user needs to create a FuseSoC core file, build with Edalize, or integrate RTL into a FuseSoC project.
Gf Ip
IP block library manager. Install, list, and query verified drop-in hardware components. Each block includes RTL, testbench, formal properties, and documentation. Example: "add a FIFO to my project", "/gf-ip add uart"
Gf Pcb
KiCad schematic and PCB generation from natural language. AI-verified drafts with DRC/ERC/AI review loop. Example: "design a breakout board for iCE40 with SPI flash and 2 PMODs"
Gf Plan
Hardware design planner - Creates comprehensive RTL implementation plans. This skill should be used when the user wants to plan a new design, architect a complex feature, or understand how to implement hardware before coding. Example requests: "plan a DMA controller", "design a UART", "architect the memory subsystem"
Gf Pnr
Place and route with nextpnr for open-source FPGA targets. Supports iCE40, ECP5, and Gowin devices. Example: "place and route for iCEBreaker", "run P&R targeting ice40"
Gf Project
Manages .gateflow/project.yaml for project-specific configuration. Auto-detects project settings or prompts user for board, HDL, and target. Used internally by other skills — not typically invoked directly.
Gf Release
GateFlow release readiness workflow. Validates plugin manifests, marketplace metadata, docs index coverage, root mirrors, release notes, and component counts before a version tag is created. Use when preparing, checking, or cutting a GateFlow plugin release.
Gf Router
Figures out what kind of digital hardware design task the user wants to do, then hands off to the right specialist. Use when the request is unclear, multi-step, or needs help deciding whether to simulate, synthesize, lint, or implement.
Gf Sim
SystemVerilog simulator with structured output for orchestration. Auto-detects DUT vs testbench, compiles with Verilator, runs simulation, and returns a parseable result block for /gf orchestration.
Gf Summary
Summarize Verilator, lint, or simulation output into a readable, actionable format. Use when the user wants to understand build output, lint errors, or simulation results from a Verilator or EDA tool run.
Gf Synth
Synthesize SystemVerilog/Verilog with Yosys. Reports area, timing, and resource utilization. Warns about unsupported SV constructs. Example: "synthesize my design for iCE40"
Gf Tui
GateFlow terminal console inspired by OpenClaw local TUI workflows. Shows workspace status, component inventory, tool health, map readiness, release readiness, and command shortcuts from one terminal surface.
Gf Viz
Terminal visualization for GateFlow codebase maps. Renders module hierarchies, FSM state diagrams, and module detail cards as interactive ASCII/Unicode art. Example requests: "visualize the codebase", "show hierarchy", "show FSM", "show module detail"
Quick start
- Choose your skills. Select individual skills above, or choose the entire pack.
- Copy the install prompt. Use Copy install prompt above the list.
- Send it to your agent. Paste into your coding agent’s chat. Your agent reviews the source and guides the setup.
Try it with your agent
After installation, start with a request like:
Use the Gf Architect skill to help with my task.
Ask me for the context you need before getting started.Requirements & license
- A coding agent that can access your project files and install skills.
- Your agent checks each skill’s instructions, dependencies, and permissions during setup.
- License details are not provided in these listings. Check the author’s terms before using the skills.